1. Field of the Invention
The present invention relates to a semiconductor test device, and particularly a semiconductor test device for evaluating an operation of a semiconductor device in a state of wafer (which will also be referred to as a “wafer level” hereinafter) as well as a semiconductor test method using the semiconductor test device.
2. Description of the Background Art
In accordance with development of a wafer level CSP (Chip Size Package) technology for processing package steps in the state of wafer, a semiconductor test device which conducts an operation test on a semiconductor device on the wafer level, which will be merely referred to as a “wafer test” hereinafter) has been of increasing importance. In a conventional semiconductor test device for the wafer test, the number of chips which can be simultaneously subjected to a parallel test, i.e., a simultaneously testable number is restricted primarily due to the following two problems.
(1) Due to a structure of a probe of a probe card for bringing a chip to be tested into electrical contact with a semiconductor test device, It is difficult to perform simultaneous contact with many chips.
(2) Since there are restrictions on numbers of power supplies on the semiconductor test device side, clock drivers and signals, it is difficult, e.g., to generate signals for simultaneously testing many chips. Further, due to the structure of the probe card, it is difficult to arrange many signal lines. This also restricts the simultaneously testable number.
For the problem (1) described above, a wafer contactor which allows the simultaneous parallel test of many chips on the wafer is now being developed. The wafer test using such a wafer contactor is specifically described in NIKKEI MICRODEVICES, February 1999, pp. 40-67.
FIG. 23 conceptually shows the wafer test using the wafer contactor.
Referring to FIG. 23, a wafer 10 (which will be merely referred to as a “test target wafer” hereinafter) having chips to be tested has a plurality of electrode pads 12 for input/output of electrical signals to and from the chips. A bump 14 is arranged on a top surface of each electrode pad 12. Bump 14 is formed of, e.g., a solder ball, and is provided for ensuring good contact between the electrode pad 12 and a board or the like to be electrically coupled thereto. Bump 14 is integrally formed on electrode pad 12.
FIG. 24 conceptually shows contact between a wafer contactor and the test target wafer.
Referring to FIG. 24, a wafer contactor 20 includes a plurality of contact terminals 22 for electrical contact with wafer 10 to be tested. When each contact terminal 22 is in contact with bump 14, it allows transmission of electrical signals to and from corresponding electrode pad 12 on wafer 10. As an example of the structure of the wafer contactor, a wafer contactor of a type using a spring probe is disclosed in NIKKEI MICRODEVICES, February 1999, page 52.
Referring to FIG. 23 again, contact terminals 22 can also be in electrical contact with board terminals 52 on a test board 50, respectively.
By employing the wafer contactor of the above structure, it is possible to make simultaneously electrical contact with the whole electrode pads required for all the chips on wafer 10 to be tested. Thereby, the problem (1) described above can be overcome.
However, it is impossible to overcome the foregoing problem (2) only by the technology of the wafer test using the wafer contactor described above, and it is difficult to improve the simultaneously testable number. According to the wafer level CSP technology, the devices are in the state of wafer when operation tests are performed, and the devices are shipped without operation test in the state of after packing. Therefore, it is important to increase the simultaneously testable number in the wafer test.
As measures for overcoming both the foregoing problems (1) and (2), such a method may be employed that each chip on the wafer to be tested is internally provided with a BIST (Built In Self Test) function, and these chips are simultaneously activated to test simultaneously the many chips on the wafer. By using the BIST function, the operation test can be conducted on each chip without using a dedicated test device such as an external memory tester, and therefore the simultaneously testable number can be improved. However, each chip must include a circuit having the BIST function, resulting in increase in chip area and cost.
According to the wafer level CSP technology, the operation test must be conducted in the wafer test for obtaining information, which is used for performing replacement repair of a defective memory cell by using a spare line provided in advance on the memory cell. This replacement repair will be referred to as “redundant repair” hereinafter. A test circuit for performing this redundant repair requires a larger area than an ordinary test circuit, which determines only PASS/FAIL of the test target chip. Therefore, the BIST system containing such test circuits further increases the required chip area.
The test circuit for the redundant repair is not used after the repairing of defective portions is performed based on the result of the operation test. Therefore, internal arrangement of the test circuits results in a waste of structure. A structure provided with a plurality of memory cores in each chip suffers from further remarkable increase in chip area because the test circuit for redundant repair is internally arranged for each memory core.
A kind of semiconductor device, which is called a system LSI, can be divided into various types, which are included in a group requiring the test circuit having the BIST function or a group not requiring it. In some types, the test circuit is not required after the redundant repair. Accordingly, it is desired to provide a method and/or structure which can flexibly determine whether the test circuit is to be internally arranged or not.